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NTD110N02R, STD110N02R
Power MOSFET
24 V, 110 A, N ? Channel DPAK
Features
? Planar HD3e Process for Fast Switching Performance
? Low R DS(on) to Minimize Conduction Loss
? Low C iss to Minimize Driver Loss
? Low Gate Charge
? Optimized for High Side Switching Requirements in
High ? Efficiency DC ? DC Converters
? AEC Q101 Qualified ? STD110N02R
? These Devices are Pb ? Free and are RoHS Compliant
V (BR)DSS
24 V
http://onsemi.com
R DS(on) TYP
4.1 m W @ 10 V
N ? Channel
D
I D MAX
110 A
MAXIMUM RATINGS (T J = 25 ° C unless otherwise noted)
Rating
Drain ? to ? Source Voltage
Gate ? to ? Source Voltage ? Continuous
Symbol
V DSS
V GS
Value
24
± 20
Unit
V
V
G
S
3
Thermal Resistance ? Junction ? to ? Case
Total Power Dissipation @ T C = 25 ° C
Drain Current
? Continuous @ T C = 25 ° C, Chip
? Continuous @ T C = 25 ° C
Limited by Package
? Continuous @ T A = 25 ° C
Limited by Wires
? Single Pulse (t p = 10 m s)
R q JC
P D
I D
I D
I D
I D
1.35
110
110
110
32
110
° C/W
W
A
A
A
A
4
1 2
3
CASE 369AA
1
2
CASE 369D
4
Thermal Resistance
? Junction ? to ? Ambient (Note 1)
? Total Power Dissipation @ T A = 25 ° C
? Drain Current ? Continuous @ T A = 25 ° C
R q JA
P D
I D
52
2.88
17.5
° C/W
W
A
DPAK
(Surface Mount)
STYLE 2
DPAK
(Straight Lead)
STYLE 2
4
Drain
Thermal Resistance
? Junction ? to ? Ambient (Note 2)
? Total Power Dissipation @ T A = 25 ° C
? Drain Current ? Continuous @ T A = 25 ° C
Operating and Storage Temperature Range
Single Pulse Drain ? to ? Source Avalanche
Energy ? Starting T J = 25 ° C
(V DD = 50 Vdc, V GS = 10 Vdc,
I L = 15.5 Apk, L = 1.0 mH, R G = 25 W )
R q JA
P D
I D
T J , T stg
E AS
100
1.5
12.5
? 55 to
175
120
° C/W
W
A
° C
mJ
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
3
Source
Maximum Lead Temperature for Soldering T L 260 ° C
Purposes, (1/8 ″ from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
1
Gate
2
Drain
Y = Year
WW = Work Week
T110N2 = Device Code
G = Pb ? Free Package
1 2 3
Gate Drain Source
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
? Semiconductor Components Industries, LLC, 2011
August, 2011 ? Rev. 10
1
Publication Order Number:
NTD110N02R/D
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